A wireless transmit/receive unit (WTRU) for second generation (2G) wireless communication systems typically includes a digital signal processor (DSP) for signal processing and symbol rate processing. The 2G WTRU usually has a control processor, (such as an advanced RISC machine (ARM)), to deal with layer 1 (L1) control and protocol stack processing.
FIG. 1 is a block diagram of a conventional WTRU 100 for 2G systems, (such as global system for mobile communication (GSM), global packet radio services (GPRS) and enhanced data rate for GSM evolution (EDGE)). The WTRU 100 includes a channel processing unit 110, a burst generation and modulation unit 120, a transmitter 130 and an antenna 140. The channel processing unit 110 includes a block coding unit 112, a convolutional encoder 114, a reordering and partitioning unit 116, and an interleaver 118. The burst generation and modulation unit 120 includes an encryption unit 122, a burst generator 124, and a modulator 126. FIG. 1 shows only a transmit side of the WTRU 100, but the WTRU 100 also includes components in a receive side that correspond to the transmit side.
Information bits 111 are first processed by the block coding unit 112, (e.g., a cyclic redundancy check (CRC) unit). Parity bits are added to the information bits 111 by the block coding unit 112. The information bits with the parity bits 113 are then processed by the convolutional encoder 114. The convolutional encoder 114 performs convolutional coding on the bits 113 to generate encoded bits 115. The encoded bits 115 are reordered and partitioned by the reordering and partitioning unit 116. The reordered and partitioned bits 117 are then interleaved by the interleaver 118. The interleaved bits 119 are encrypted by the encryption unit 122. The encrypted bits 123 are sent to the burst generator 124. The burst generator 124 generates bursts 125 from the encrypted bits 123. Burst multiplexing is also performed by the burst generator 124. The bursts 125 are then processed by the modulator 126. Modulated symbols 127 are then transmitted by the transmitter 130 via the antenna 140.
FIG. 2, which is taken from third generation partnership project (3GPP) technical specification (TS) 45.003 section 2.1, shows processing of information bits for some of the channels in GSM, GPRS and EDGE. A plurality of channels are supported in 2G systems. FIG. 2 shows processing of information bits for a traffic channel for enhanced full rate speech (TCH/EFS), a traffic channel for full rate speech (TCH/FS), a traffic channel for half rate speech (TCH/HS), a data traffic channel, and a packet data traffic channel (PDTCH).
Referring to FIGS. 1 and 2, processing of information bits for a TCH/FS is explained as an illustrative example. A speech coder (not shown in FIG. 1), either full rate or enhanced full rate, delivers to the channel processing unit a sequence of blocks of data. In case of a TCH/FS or TCH/EFS, one block of data corresponds to one speech frame. Each block contains 260 information bits, including 182 class 1 bits (protected bits) and 78 class 2 bits (notprotected bits). The 260 bits of each block is processed by the block coding unit. The first 50 class 1 bits are protected by three (3) parity bits for error detection. The class 1 input bits and parity bits are reordered and four (4) tailing bits are appended to the end. The block coding unit outputs 267 bits including three parity bits and four tailing bits. Class 1 bits of the 267 bits are encoded with the ½ rate convolutional coding by the convolutional encoder. The convolutional encoder outputs 456 bits of encoded bits. The 456 encoded bits are reordered and partitioned by the reordering and partitioning unit. The reordering and partitioning unit outputs 8 blocks of bits. The 8 blocks of bits are then block diagonally interleaved by the interleaver. The reordering and interleaving are performed based on a predefined table.
As a dual-mode WTRU supporting both 2G and third generation (3G) services is increasingly used in the market, physical resources need to be shared for 2G and 3G processing for cost reduction and power saving. As data rates increase, and modulation techniques and receiver algorithms become more complex, the processing requirements that must be supported by the DSP continue to grow. Other functions supported by the DSP, such as voice codecs, are also becoming more complex. Simply increasing the frequency of the DSP to support the added functionality will create other problems, including higher power dissipation, increased demands on the memory subsystem.
A potential solution to this problem is to offload some of the processing from the DSP into a hardware accelerator. Traditional hardware accelerators are controlled by the DSP, usually by using direct memory access (DMA) techniques or programmed I/O to get input data into the accelerator, register writes to start the accelerator, and DMA techniques or programmed I/O to access the results of the accelerator. Traditional hardware accelerators are typically “hardwired” to perform a specific function, so moving functionality from a DSP to a hardware accelerator results in a loss of flexibility (compared to software running on the DSP) and the need for major hardware changes if a change in functional requirements occurs.